This invention relates generally to computer systems and more particularly to reduced instruction set computer processors.
As it is known in the art, a computer system generally includes a central processing unit for processing an instruction stream. The computer system is a hardware device, typically composed of a number of discrete functional units. The instruction stream is stored in a memory and comprises a set of instructions and data which is recognizable by the hardware residing in the computer system. During operation, each instruction as it is retrieved from memory is decoded to determine the specific function performed by the instruction. Once decoded, the hardware executes the desired function. Thus it can be seen that there is a direct relationship between the instruction set of the computer and the architecture of the computer.
In order to create an instruction stream to run on the computer, each software program that is to execute on the computer system must be decomposed into a series of instructions from the instruction set of the computer. The procedure of breaking down a higher level language computer program into a series of instructions from a given instruction set is typically performed by a software program known in the art as a compiler. Generally the compiler receives as inputs the higher level software language, the available instruction set, and perhaps certain characteristics of the operating computer, i.e. such as the number of working registers available in the computer system. As the compiler reads, or parses, the higher level software program, it distinguishes groups of commands that may be performed by different instructions of the instruction set.
There are two types of instruction sets and associated architectures commonly used in the art. A first type, known as a complex instruction set, is executed on a complex instruction set computer (CISC). The complex instruction set includes specialized instructions to handle common types of high level software commands. In determining which instructions were included in the CISC instruction set, an analysis of particular applications whose performance could be increased by grouping instructions was performed, and a set of instructions was developed. For example, the VAX.TM. instruction set includes the instruction "Add One and Branch if Less than or Equal" (AOBLEQ) for use during computer loop operations. During processing of this one instruction, values are added, compared against a given value, and a potential branch operation is performed. Thus it can be seen that the complex instruction set serves to increase computer performance for groups of commonly used instructions.
However, there are a number of drawbacks associated with the CISC architecture. When using a complex instruction set, the decode function of the computer system must be able to recognize a wide variety of functions. As a result, the decode logic, while time critical for purposes of performance, grows to be quite complex. However, not every one of the complex instructions are used for each software program, and thus much of the decode logic functionality is seldom used during operation. A second drawback of the CISC architecture arises from the fact that the complex instructions are often of different lengths. That is, each instruction could consist of any number of operands, and take any number of cycles to execute. Thus, when parsing a CISC instruction, it is often difficult to determine when the decode of an instruction was close to completion and when the next instruction in the sequence could be retrieved. This uncertainty associated with instruction length makes the instruction decode logic of the complex instruction set computer even more difficult to design and thus may decrease the overall processor performance.
As a result of the drawbacks associated with the CISC instruction set, a reduced instruction set computer (RISC) began to gain wide acceptance by providing increased performance with minimal design complexity. The reduced instruction set comprised a minimal number of easily implementable, one-cycle instructions, each having the same length. The contents of the reduced instruction set were determined by evaluating a wide range of applications to determine which instructions were most commonly required. Typical reduced instruction sets comprised a LOAD instruction, a STORE instruction, and a handful of arithmetic instructions. The higher level language software program were decomposed into a series of these short instructions by the compiler. As a result, the complexity of the decode logic was greatly reduced and accordingly the performance of RISC computers for certain application exceeded that of CISC computers.
However, there remained drawbacks with the reduced instruction set computers. Although the RISC architecture was adequate for handling a wide range of applications, for a given particular application, with a specific implementation need, the RISC computer performance often fell short of that of the CISC computers. For example, referring again to the AOBLEQ instruction, to perform such an operation in a reduced instruction set computer requires the execution of numerous instructions from the RISC instruction set.
Accordingly, it would be desirable to in some way combine the performance advantages gained by the RISC architecture with the flexibility provided by the CISC architecture to allow for optimization of the hardware/software interface.